SimDE MODEL

SimDE™ MODEL Release 201512 (NEW) 

- Simulation Development Environment for Modeling

SimDE™MODEL Introduction

SimDE™ MODEL Datasheet

 

SimDE™ MODEL Overview

Simulation is becoming increasingly important for High-Speed system designs. It can help optimize your design performance, reduce your design cycle, lower your prototype cost and accelerate your design to the market. Electrical I/O modeling is the starting point for your advanced chip and system simulations. It enables faster and more accurate simulations.
SimDE™ MODEL provides a graphical model development and validation environment. It gives a direct method for model development and validation. It focuses on automated SI model generation and validation processes (IBIS and SPICE macromodeling in this version and Verilog-A / VHDL-AMS in the future).

 

Create more accurate models, more quickly.

IBIS 5.0 PDN [Composite Current] and [ISSO_*] Features with Initial Delay Trim functionalities

Integrated with HSpice, Spectre, Eldo. MSIM and TISpice3

Model Generation and Validation together seamlessly

 

 

 

IBIS Model Generation and Validation

SimDE™ MODEL provides an automated IBIS buffer model generation and validation process. It includes a graphical interface for mapping the SPICE buffer nodes, as well as using the schematic type editing mode for other node settings. It automatically runs the compatible simulators (supports Synopsys HSpice, Cadence Spectre, Mentor Eldo, Legend MSIM and TISpice) to extract the buffer's behavior from the Spice buffer. There is no need for manual editing during the process.

SimDE™ MODEL has a seamless validation process for IBIS buffer model generation. It remembers all the settings for the Spice model when generating the IBIS buffer and uses them for your IBIS model validation on your own topologies. It also provides a detailed DPI (Differential Peak Index) and DAI (Differential Average Index), and reports any differences between the Spice and IBIS buffer simulations as well as the visual waveform inspection.

SimDE™ MODEL contains:

  • Automatic Spice buffer node mapping capability
  • Graphical node setting capability
  • Automatic Spice to IBIS buffer extraction process
  • Auto Die-Capacitance extraction option for both driving and receiving mode.
  • Capable for All IBIS Input / Output / IO model types and differential buffers (Pseudo, half and true differential pair) extractions
  • Easy setup for Typical / Minimum / Maximum corner extractions
  • The best behavial curve representation algorithm build-in
  • Built-in IBIS standard buffer test fixtures and IBIS validation simulator
  • Supports HSpice, Spectre, Eldo, MSIM and TISpice3 integrations
  • Extraction using existing data for IBIS and IBIS differential models
  • IBIS 5.0 PDN feature auto-extractions
  • IBIS buffer model validation sheet with freedom of topology settings
  • Detail validation reports with Differential Peak Index (DPI) and Differential Average Index (DAI)
  • IBIS buffer curves visual inspection and report for On-die termination, non-monotonic and load-line crossing verification. (SignalMeth™ IBIS Application Module)
  • Ease-of-use IBIS File generation wizard with Model Selector Builder
  • Customizable stimulus settings for more accurate IBIS buffer model development
  • Supports True-differential current-mode IBIS buffer extractions
  • Simulation-only option to enable large number extraction simulations using queued simulation scripts
  • batch-mode operations for large numbers of buffers in one project
  • Initial Delay Trim functionality for Over Clocking IBIS simulations
  • VT/IT curve length and maximum point controls
  • Auto-Set feature for differential VT fixture setting
  • Batch-mode Model(MDL) creation in the project using option setting file for programmable buffer options. 
  • Support IBIS Series_switch model extraction and validations
  • Support S2I project model import
  • C_comp re-order functionality
  • Large IV/VT mismatch Stop/Continue Warning

Spice Macromodel Generation, Fitting and Validation

SimDE™ MODEL also provides an integrated flow for Spice Macromodel Generation, fitting and validation. It allows a user to start from scratch or start from the base elements, using our integrated standard library elements or elements you made as black-boxes. Its hierarchy structure will give the user a clean graphical structural view from the different levels.
The fitting procedure allows the user to load the Golden waveform for the macromodel optimization process. It can swing many parameters and find the best settings for the case that fits the Golden source the best. 
The validation process take place in an easy to use environment for verifying the macromodel that you just built for a specific load validation. You may also import 3rd party models for validation. 
The Spice macromodel is powerful and fast. It can virtually model everything you may need.

Macromodeling is the alternative in advanced method for IP protected, high performance device modeling.